1. Field of the Invention
The present invention relates to a dynamic random access memory (DRAM) which has synchronous data transfer means.
2. Description of the Related Art
Two of the important points in designing a largescale integrated circuit (LSI) are an increase in the operating speed at which the LSI operates, and a reduction in the power the LSI consumes. The higher the integration density of the LSI, the greater the capacitance and resistance of the data lines which connects the circuit blocks of the LSI. When the LSI data lines have a great capacitance and a high resistance, the performance of the LSI decreases. To set the LSI performance at a sufficiently great value despite the great capacitance and high resistance of the data lines, a data transfer control system is used. This system comprises a differential amplifier connected between an input data line and an output data line of the LSI, and an equalizing circuit connected to the output terminal of the differential amplifier. First, the equalizing circuit resets the data on the output data line. Then, the data is transferred from the input data line to the output data line.
The data transfer control system described above makes it possible to transfer data at high speed, even if the data lines, in particular the output data lines, have a large capacitance or a high resistance. The reason why will be explained briefly. If new data is transferred from the input data line to the output data line, with the old data remaining on the data output line, the differential amplifier needs to drive the output data line, thereby to invert the old data and form new data. In order to perform this task, the amplifier must have a great drivability. Hence, if the output data line has a great capacitance or a high resistance, data cannot be transferred at high speed. In the data transfer control system, data can be transferred at high speed even if the differential amplifier has no great drivability, since the equalizing circuit resets the output data line prior to the data transfer.
Even if the data transfer control system is used, however, the transfer of the new data is delayed if it takes a long time to equalize the output data line. The delay in transferring the new data is a bar to high-speed operation and makes a great problem to a recently developed large-chip LSI, in particular a DRAM comprising data lines which are thin and long and, hence, have a great capacitance or a high resistance. To be more specific, the operating speed of the I/O data buffer incorporated in a DRAM, for transferring data to, and receiving data from, external devices, is very important.
As has been described, in the great problem with the I/O data buffer used in the conventional large-scale DRAM, it takes a long time to equalize the data lines, inevitably reducing the speed of data transfer.